1. Field of the Invention
The present invention relates to semiconductor devices and methods for manufacturing the same, and more particularly, to semiconductor devices having metal silicide conductive layers, semiconductor devices having contact plugs self-aligned with a lower structure which is comprised of the conductive layers, and a method for manufacturing the semiconductor devices.
2. Description of the Related Art
As the integration density of semiconductor devices continues to increase, distance from contact holes that connect lower and upper interconnection layers to surrounding interconnections, decreases with an increase in the aspect ratio of the contact holes. Thus, highly integrated semiconductor devices adopting a multilayered interconnection structure require more accurate and strict processing conditions in contact hole formation by using photolithography. In particular, in manufacturing semiconductor devices having a design rule of 0.25 xcexcm or less, current lithography techniques are not sufficient to reproducibly perform desirable processes with the same accuracy.
In order to overcome limitations of photolithography in the formation of contact holes, a self-alignment technique has been suggested for forming contact holes. For example, a self-alignment technique has suggested nitride spacers be used as an etch stop layer in the formation of self-aligned contact holes.
In the conventional self-alignment technique, first a lower structure, for example, a conductive layer such as a gate electrode having a rectangular section, is formed on a semiconductor substrate via patterning by a general photolithography process, and then a layer of nitride is deposited on the entire surface of the conductive layer. Then, an etchback process is carried out on the resulting structure so as to form nitride spacers, and then interlayer dielectric (ILD) oxide films are formed thereon. Thereafter, a photoresist pattern is formed on the ILD films for exposing contact holes, and the exposed ILD films are etched to form self-aligned contact holes.
In the conventional self-aligned contact hole formation, the ILD films are etched with a high selectivity with respect to the nitride spacers to form the contact holes. During the etching process, carbon rich carbon fluoride gases capable of producing a large amount of polymer, for example, C4F8 or C5F8, are used so as to increase the selectivity.
However, if the etching conditions are determined to increase selectivity, the amount of polymer produced by the etching increases, so that the etching process may be interrupted, resulting in incomplete contact holes. Meanwhile, when the selectivity between the ILD films and the nitride spacers is decreased, complete contact holes can be formed without the interrupt due to the polymer. However, when the selectivity is low, the nitride spacers may be etched together with the ILD films during the etching process. Accordingly, the width of the remaining nitride spacers is too small to secure a desired insulation length from the sidewalls of conductive layers. Thus, it is prone to cause short between self-aligned contacts in the contact holes and the conductive layers.
In fabrication of highly integrated semiconductor devices having a design rule of 0.25 xcexcm or less, when forming self-aligned contact holes over conductive layers such as gate electrodes or bit lines, which have an etch stop layer such as a nitride layer on the sidewalls thereof, an insulation thickness margin between the conductive layers and self-aligned contacts in the contact holes is not sufficient. A possible solution for overcoming this problem may be to lower the selectivity between ILD films and the etch stop layer in the self-aligned contact hole formation. However, the etch stop layer itself is removed or damaged with the low selectivity, so that it is difficult even to get a minimum insulation width at the edges of the conductive layer, increasing the possibility that the edges of the conductive layer directly be exposed to the contact holes.
Thus, in the self-aligned contact formation for manufacturing highly integrated semiconductor devices, the process margin is small even under optimal processing conditions, and thus it is difficult to reproducibly produce devices with the same accuracy.
It is an object of the present invention to provide semiconductor devices allowing an increased process margin, in which a desired insulation length between a lower conductive layer and self-aligned contacts can be ensured in self-aligned contact hole formation for manufacturing highly integrated semiconductor devices.
It is another object of the present invention to provide semiconductor devices having contact plugs self-aligned with a lower structure having the above configuration.
It is still another object of the present invention to provide methods for manufacturing the semiconductor devices.
In an embodiment, the present invention provides a semiconductor device comprising: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.
Preferably, the semiconductor device further comprises contact plugs filling self-aligned contact holes in a self-aligning manner with the gate structures, the self-aligned contact holes exposing both the first insulation spacers and the active regions of the semiconductor device.
Preferably, the semiconductor device further comprises: a specific circuit having a predetermined function formed on the semiconductor substrate; a redundant circuit formed with the same function as that of the specific circuit on the semiconductor substrate; and a fuse formed with the same structure as that of the gate structures on the first insulation layer, the fuse being melted and removed for replacing a defective circuit with the redundant circuit.
Preferably, the semiconductor device further comprises: a planarized first interlayer dielectric (ILD) film pattern formed on the second insulation layer; bit lines formed on the first ILD film pattern; and a third insulation layer formed to cover the top surface of the bit lines, wherein the bit lines comprise conductive patterns and the upper edges of the conductive patterns are chamfered.
The semiconductor device may further comprise second insulation spacers on the sidewalls of the bit lines and on the sidewalls of the third insulation layer.
Preferably, the semiconductor device further comprises: a second ILD film pattern on the third insulation layer; and contact plugs filling self-aligned contact holes in a self-aligning manner with the bit lines, the self-aligned contact holes exposing both the second insulation spacers and an active region of the semiconductor device.
Preferably, the semiconductor device further comprises: a second ILD film pattern on the third insulation layer; and contact plugs filling self-aligned contact holes in a self-aligning manner with the gate structures and the bit lines, the self-aligned contact holes exposing both the first and second insulation spacers and an active region of the semiconductor device.
In another embodiment, the present invention provides a semiconductor device comprising: an ILD film pattern formed on a semiconductor substrate; bit lines formed on the ILD film pattern, the bit lines comprising conductive patterns and the upper edges of the conductive patterns being chamfered; and an insulation layer formed with a first width W on the bit lines, wherein the sidewalls of the insulation layer overhang the upper edges of the bit lines.
In another aspect of the object, the present invention provides a method of manufacturing a semiconductor device, comprising forming a first conductive layer on a semiconductor substrate. A second conductive layer is formed on the first conductive layer, and first mask patterns are formed on the second conductive layer, the first mask patterns partially exposing the top surface of the second conductive layer. Then, part of the second conductive layer is isotropically etched using the first mask patterns as an etch mask, so as to form first undercut regions exposing the edges of the bottom of the first mask patterns. Then, the remaining second conductive layer is anisotropically etched using the first mask patterns as an etch mask, so as to form second conductive layer patterns which have lower edges substantially perpendicular to the major surface of the semiconductor substrate, and chamfered upper edges. The first conductive layer is isotopically etched using the first mask pattern as an etching mask, so as to form first conductive layer patterns.
Preferably, forming the first undercut regions are carried out by a dry or wet etching technique. When the dry etching is adopted to form the first undercut regions, at least one gas selected from the group consisting of CF4, C2F6, CHF3, CO, Ar, O2, N2 and Hexe2x80x94O2 may be used. When the wet etching is adopted to form the undercut regions, a NH4OH, H2O2 and H2O mixture may be used.
Preferably, forming the first mask patterns comprises: forming an insulation layer on the second conductive layer; forming photoresist pattens on the insulation layer; and anisotropically etching the insulation layer using the photoresist patterns as an etch mask, so as to form the first mask patterns.
Preferably, forming the first mask patterns is followed by removing the photoresist patterns via ashing, and the formation of the first undercut regions is simultaneously carried out with the ashing of the photoresist patterns. Alternatively, the formation of the first undercut regions may be continuously carried out immediately after the ashing of the photoresist patterns in the same chamber.
Preferably, after forming the first mask patterns, the method of manufacturing the semiconductor device further comprises: removing the photoresist patterns via ashing; and removing residue which results from the ashing, via a stripping process, and forming the first undercut regions is continuously carried out immediately after the stripping process in the same chamber.
Preferably, the semiconductor device manufacture may further comprise forming an insulation layer on at least the sidewalls of the first and second conductive layer patterns and the first mask patterns. A planarized ILD film is then formed on the insulation layer, and the first ILD film is selectively etched so as to form self-aligned contact holes exposing an active region of the semiconductor substrate.
Preferably, forming the first conductive layer patterns is followed by removing the second conductive layer patterns by a predetermined width from the exposed edges thereof so as to form recessed second conductive layer patterns which have a maximum width less than the width of the first mask patterns and the first conductive layer patterns.
Preferably, the semiconductor device manufacture further comprises forming an insulation layer on at least the sidewalls of the first conductive layer pattern, on the sidewalls of the recessed second conductive layer patterns and on the sidewalls of the first mask patterns. Then, a planarized ILD film is formed on the insulation layer, and the first ILD film is selectively etched so as to form self-aligned contact holes exposing an active region of the semiconductor substrate.
Preferably, the semiconductor device manufacture further comprises forming a first interlayer dielectric (ILD) film which completely covers the first mask patterns. Bit lines are formed on the first ILD film. For the formation of the bit lines, a third conductive layer is formed on the first ILD film, and second mask patterns are formed on the third conductive layer, the second mask patterns exposing part of the top surface of the third conductive layer. Then, part of the exposed third conductive layer is isotropically etched using the second mask patterns as an etch mask so as to form second undercut regions exposing the edges of the bottom of the second mask patterns. Then, the remaining part of the exposed third conductive layer is anisotropically etched using the second mask patterns as an etch mask so as to form third conductive layer patterns which have lower edges substantially perpendicular to the major surface of the semiconductor substrate, and chamfered upper edges.
The semiconductor device manufacture may further comprises forming first insulation spacers on the sidewalls of the first and second conductive layer patterns and the first mask patterns. Then, second insulation spacers are formed on the sidewalls of the third conductive layer patterns and the second mask patterns. Preferably, the semiconductor device manufacture further comprises forming a second ILD film to cover the second mask patterns. The second and first ILD films are selectively etched so as to form self-aligned contact holes exposing the first and second insulation spacers and active region of the semiconductor substrate. Then, the self-aligned contact holes are filled with a conductive material so as to form contact plugs in a self-aligning manner with the first and second conductive patterns and the bit lines.
According to the present invention, a desired insulation length can be ensured without the degradation of the electrical properties of devices, by the insulation spacers with a sufficient width between the gate structures and the contact plugs self-aligned therewith. Thus, the present invention can be adapted to the manufacture of highly integrated semiconductor devices having a design rule of 0.25 xcexcm or less.
Also, when the contact plugs are self-aligned with both the gate structures and the bit lines, the present invention can provide the bit lines with the chamfered upper edges, so that the spacers on the sidewalls of the bit lines can provide a sufficient width after etching to form self-aligned contact holes, and thus a desired insulation length between the bit lines and the contact plugs can be ensured without adverse effects on the electrical properties of devices.
In addition, in the method for manufacturing the semiconductor device according to the present invention, the metal silicide layer patterns with the chamfered upper edges can be formed without additional complicated processing. That is, the chamfered upper edges of the metal silicide layer patterns are formed during the process for ashing and stripping the photoresist patterns, which a basic processes included in general semiconductor device fabrication processes so as to remove the photoresist patterns used to pattern the metal silicide layers. Thus, by effectively using the essential processes in semiconductor device manufacture, undercut regions can be formed through a minimum number of processes, which allows the metal silicide layer patterns to have the chamfered upper edges.